OVER THE COURSE OF THIS PROGRAM, NUVOTRONICS WILL DEVELOP OF A ROBUST WAFER-LEVEL CHIP INTEGRATION TECHNOLOGY USING OUR PROPRIETARY POLYSTRATA PROCESS TO ENABLE SUB-MILLIMETER MONOLITHIC INTEGRATED CHIP (IC). THIS NEW PROCESS OFFERS A DISRUPTIVE WAFER LEVEL PACKAGING, CAPABLE OF MONOLITHICALLY INTEGRATING DIS-SIMILAR SEMICONDUCTOR SUBSTRATES SUCH AS SILICON, SIGE, GAAS, GAN AND INP WHILE REDUCING THE INTERCONNECTS LOSSES AND REMOVING THE NEED WIREBONDS. USING THE 8 POLYSTRATA PROCESS ON WAFER, DIFFERENT CHIPS (LOW NOISE AMPLIFIERS, PAS, MIXERS, SWITCHES) CAN BE MONOLITHICALLY INTEGRATED AND INTERCONNECTED USING COPPER MICROFABRICATION PROCESS TO CREATE A IC MODULE. TO DEMONSTRATE THE PERFORMANCE OF THE NEW WAFER LEVEL PACKAGING APPROACH, DURING THE PHASE II, NUVOTRONICS WILL LEVERAGE THE NEW PROCESS TO FABRICATE A COMPLETE W-BAND MONOLITHIC RADIOMETER IC. THE POLYSTRATA IC WILL BE SURFACE MOUNTABLE USING INDUSTRY STANDARD REFLOW PROCESS AND WILL NOT REQUIRE WIREBONDING, HIGH ACCURACY PLACEMENTS OR EXPENSIVE RF CIRCUIT BOARD. NUVOTRONICS AIMED IN THIS PROGRAM A REVOLUTIONIZING THE WAY MM-WAVE CIRCUIT ARE FABRICATED BY IMPROVING THE INTERCONNECTION PERFORMANCE UP TO 220 GHZ AND SIGNIFICANTLY REDUCING THE PACKAGING COST.