SEU/SEL RESISTANT ULTRA-LOW POWER ASYNCHRONOUS PROCESSOR DESIGN FOR LOW-TEMPERATURE APPLICATIONS THIS PHASE I SBIR PROPOSAL SEEKS FUNDING TO DEVELOP A RADIATION-HARDENED CIRCUIT ARCHITECTURE TO ACHIEVE SEU AND SEL IMMUNITY BY USING DELAY-INSENSITIVE ASYNCHRONOUS LOGIC, AND TO DEMONSTRATE ITS FEASIBILITY, EFFECTIVENESS, AND EFFICIENCY. FURTHER, EARLY STUDIES REVEAL THAT AN OPERATIONAL TEMPERATURE RANGE OF 2K TO 400K WILL BE HIGHLY FEASIBLE. DELAY-INSENSITIVE ASYNCHRONOUS LOGIC REMOVES THE CONCEPT OF A GLOBAL CLOCK BY INCORPORATING HANDSHAKING PROTOCOLS TO CONTROL THE CIRCUIT. THE HANDSHAKING PROTOCOLS ALLOWS FOR FLEXIBLE TIMING REQUIREMENTS, HIGH POWER EFFICIENCY, AND LOW NOISE/EMISSION GENERATION. THE FLEXIBLE TIMING NATURE OF DELAY-INSENSITIVE LOGIC MAKES THIS TYPE OF CIRCUITS AN EXCELLENT CANDIDATE FOR MITIGATING RADIATION EFFECTS IN DIGITAL ELECTRONICS. COMPARED TO THE EXISTING RADIATION-HARDENING TECHNIQUES, THE PROPOSED SOLUTION HAS SEVERAL SUBSTANTIAL BENEFITS INCLUDING COST EFFICIENCY, SEU/SEL IMMUNITY WITHOUT WEAK POINTS, AND THE ABILITY TO RETAIN DATA DURING POWER CYCLING WHILE MITIGATING SEL. IN ADDITION, SIGNIFICANTLY IMPROVED SUPPLY VOLTAGE VARIATION SUSTAINABILITY AND SECURITY AGAINST POWER-BASED SIDE-CHANNEL ATTACKS CAN ALSO BE ACHIEVED.